Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge
| dc.contributor.author | Oltra-Oltra, Josep | |
| dc.contributor.author | Vallejo, Bernardo | |
| dc.contributor.author | Madrenas, Jordi | |
| dc.contributor.author | Mata-Hernández, Diana | |
| dc.contributor.author | Zapata, Mireya | |
| dc.contributor.author | Sato, Shigeo | |
| dc.date.accessioned | 2022-06-20T02:47:03Z | |
| dc.date.available | 2022-06-20T02:47:03Z | |
| dc.date.issued | 2021 | |
| dc.description.abstract | This paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). As such, the hardware implementation of Single Instruction Multiple Data (SIMD)-based Spiking Neural Network (SNN) requires the development of user-friendly and efficient toolchain in order to maximise the potential that the architecture brings. By using a novel SNN architecture, a custom designed hardware/software toolchain has been developed. The toolchain performance has been experimentally checked on a Band-Pass Filter (BPF), obtaining optimized code and dat | es |
| dc.identifier.uri | https://ieeexplore.ieee.org/document/9401615 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.14809/3264 | |
| dc.language.iso | eng | es |
| dc.publisher | Proceedings - IEEE International Symposium on Circuits and Systems. Volume 2021-May. 3rd IEEE International Symposium on Circuits and Systems, ISCAS 2021. Daegu. 22 May 2021 through 28 May 2021 | es |
| dc.rights | openAccess | es |
| dc.rights.uri | https://creativecommons.org/licenses/by/4.0/ | es |
| dc.title | Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge | es |
| dc.type | article | es |
