Please use this identifier to cite or link to this item: https://repositorio.uti.edu.ec//handle/123456789/3439
Title: PSoC-Based Real-Time Data Acquisition for a Scalable Spiking Neural Network Hardware Architecture
Authors: Zapata, Mireya
Balaji, Upasana
Madrenas, Jordi
Issue Date: 2018
Publisher: 2018 IEEE 3rd Ecuador Technical Chapters Meeting, ETCM 2018. 17 December 2018. 3rd IEEE Ecuador Technical Chapters Meeting, ETCM 2018. Cuenca. 15 October 2018 through 19 October 2018
Abstract: Data acquisition for monitoring the spiky activity of large-scale SNN hardware architectures are a challenge due to their time constraints, complexity, large logic size, and so on. This paper presents a versatile PSoC-Based Data Acquisition prototype, where a specialized Master Device is used for this purpose. It benefits from the heterogeneous nature of SoC platforms that allows it to host programmable logic together with a hard-core ARM processor integrating memory and a variety of peripherals in a single chip. The presented design enables monitoring the performance of a multi-chip neural network through a single Ethernet interface in a hardware and software co-design, which is combined with an application developed in Python that allows the visualization on the PC of a dynamic raster plot of neural activity. In addition, an example of full platform functionality is shown. © 2018 IEEE.
URI: https://ieeexplore.ieee.org/document/8580286
http://repositorio.uti.edu.ec//handle/123456789/3439
Appears in Collections:Artículos Científicos Indexados

Files in This Item:
There are no files associated with this item.


This item is licensed under a Creative Commons License Creative Commons