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Campo DC | Valor | Lengua/Idioma |
---|---|---|
dc.contributor.author | Zapata, Mireya | - |
dc.contributor.author | Balaji, Upasana | - |
dc.contributor.author | Madrenas, Jordi | - |
dc.date.accessioned | 2022-06-30T16:31:11Z | - |
dc.date.available | 2022-06-30T16:31:11Z | - |
dc.date.issued | 2018 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/8580286 | - |
dc.identifier.uri | http://repositorio.uti.edu.ec//handle/123456789/3439 | - |
dc.description.abstract | Data acquisition for monitoring the spiky activity of large-scale SNN hardware architectures are a challenge due to their time constraints, complexity, large logic size, and so on. This paper presents a versatile PSoC-Based Data Acquisition prototype, where a specialized Master Device is used for this purpose. It benefits from the heterogeneous nature of SoC platforms that allows it to host programmable logic together with a hard-core ARM processor integrating memory and a variety of peripherals in a single chip. The presented design enables monitoring the performance of a multi-chip neural network through a single Ethernet interface in a hardware and software co-design, which is combined with an application developed in Python that allows the visualization on the PC of a dynamic raster plot of neural activity. In addition, an example of full platform functionality is shown. © 2018 IEEE. | es |
dc.language.iso | eng | es |
dc.publisher | 2018 IEEE 3rd Ecuador Technical Chapters Meeting, ETCM 2018. 17 December 2018. 3rd IEEE Ecuador Technical Chapters Meeting, ETCM 2018. Cuenca. 15 October 2018 through 19 October 2018 | es |
dc.rights | openAccess | es |
dc.rights.uri | https://creativecommons.org/licenses/by/4.0/ | es |
dc.title | PSoC-Based Real-Time Data Acquisition for a Scalable Spiking Neural Network Hardware Architecture | es |
dc.type | article | es |
Aparece en las colecciones: | Artículos Científicos Indexados |
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