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    dc.contributor.authorOltra-Oltra, Josep-
    dc.contributor.authorVallejo, Bernardo-
    dc.contributor.authorMadrenas, Jordi-
    dc.contributor.authorMata-Hernández, Diana-
    dc.contributor.authorZapata, Mireya-
    dc.contributor.authorSato, Shigeo-
    dc.date.accessioned2022-06-20T02:47:03Z-
    dc.date.available2022-06-20T02:47:03Z-
    dc.date.issued2021-
    dc.identifier.urihttps://ieeexplore.ieee.org/document/9401615-
    dc.identifier.urihttp://repositorio.uti.edu.ec//handle/123456789/3264-
    dc.description.abstractThis paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). As such, the hardware implementation of Single Instruction Multiple Data (SIMD)-based Spiking Neural Network (SNN) requires the development of user-friendly and efficient toolchain in order to maximise the potential that the architecture brings. By using a novel SNN architecture, a custom designed hardware/software toolchain has been developed. The toolchain performance has been experimentally checked on a Band-Pass Filter (BPF), obtaining optimized code and dates
    dc.language.isoenges
    dc.publisherProceedings - IEEE International Symposium on Circuits and Systems. Volume 2021-May. 3rd IEEE International Symposium on Circuits and Systems, ISCAS 2021. Daegu. 22 May 2021 through 28 May 2021es
    dc.rightsopenAccesses
    dc.rights.urihttps://creativecommons.org/licenses/by/4.0/es
    dc.titleHardware-software co-design for efficient and scalable real-time emulation of SNNs on the edgees
    dc.typearticlees
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