Please use this identifier to cite or link to this item: https://repositorio.uti.edu.ec//handle/123456789/3307
Title: Characterizing High-Speed Serial Transceivers for a Multi-processor Parallel Architecture
Authors: Zapata, Mireya
Vallejo-Mancero, Bernardo
Topon-Visarrea, Blanca
Issue Date: 2021
Publisher: Advances in Intelligent Systems and Computing. Volume 1269 AISC, Pages 295 - 300. 3rd International Conference on Human Systems Engineering and Design: Future Trends and Applications, IHSED 2020. Pula. 22 September 2020 through 24 September 2020
Abstract: Emulation of large scale neural networks is a growing research field that tries to understand how the brain works. Different approaches based on hardware and software have been developed for this purpose. However, in this paper, we focus on dedicated parallel hardware implemented with FPGA. In this context, brain connectivity is one of the biggest challenges to overcome for neuromorphic circuits. To establish an efficient communication link in multi-FPGA architectures, high-speed serial transceivers GTX are an excellent alternative. Through hardware tests with Kintex 7 and Zynq ZC706 platforms, we compare eye pattern, and BER results, in order to obtain the optimal line rate to establish communication between both boards. The maximum transmission speed achieved without signal degradation was 5 Gpbs.
URI: https://link.springer.com/chapter/10.1007/978-3-030-58282-1_47
http://repositorio.uti.edu.ec//handle/123456789/3307
Appears in Collections:Artículos Científicos Indexados

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