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dc.contributor.authorCastro, Cristhian-
dc.contributor.authorZapata, Mireya-
dc.date.accessioned2022-06-20T19:11:23Z-
dc.date.available2022-06-20T19:11:23Z-
dc.date.issued2021-
dc.identifier.urihttps://link.springer.com/chapter/10.1007/978-3-030-51328-3_57-
dc.identifier.urihttp://repositorio.uti.edu.ec//handle/123456789/3312-
dc.description.abstractThe high performance of FPGA devices allows moving traditionally analog stages into the digital world. This article introduces the implementation of a Digital Up-Converter, which is part of a broadband system. This system uses polyphase decomposition to achieve 5GSPS sampling rates. The transmitter uses 7 data channels each divided into 16 phases of 312.5 MHz. The model implements a DDS suitable to the specific needs of the system, keeping the frequencies of carrier’s constant, which reducing resource utilization and simplifying the architecture of the DDS. The model is coded in Verilog and simulated at RTL and Gate level. In order to validate the output, it is compared to a finite precision model in Matlab. The maximum clock frequency is measured using time analysis, obtaining adequate results in the operation and utilization of hardware resources.es
dc.language.isoenges
dc.publisherAdvances in Intelligent Systems and Computing. Volume 1213 AISC, Pages 414 - 421. AHFE Virtual Conferences on Software and Systems Engineering, and Artificial Intelligence and Social Computing, 2020. San Diego. 16 July 2020 through 20 July 2020es
dc.rightsopenAccesses
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/es
dc.titleEfficient FPGA Implementation of Direct Digital Synthesizer and Digital Up-Converter for Broadband Multicarrier Transmitteres
dc.typearticlees
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